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some more arm-simds

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This commit is contained in:
Joachim Schöberl 2021-01-31 16:31:47 +01:00
parent 18f5a933a9
commit 9a9828d3af
1 changed files with 43 additions and 23 deletions
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64
libsrc/core/simd_arm64.hpp
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@ -10,14 +10,13 @@ namespace ngcore
public: public:
SIMD (int i) SIMD (int i)
{ {
mask[0] = i > 0; mask[0] = i > 0 ? -1 : 0;
mask[1] = i > 1; mask[1] = i > 1 ? -1 : 0;
} }
SIMD (bool i0, bool i1) { mask[0] = i0; mask[1] = i1; } SIMD (bool i0, bool i1) { mask[0] = i0 ? -1:0; mask[1] = i1 ? -1 : 0; }
SIMD (SIMD<mask64,1> i0, SIMD<mask64,1> i1) { mask[0] = i0[0]; mask[1] = i1[0]; } SIMD (SIMD<mask64,1> i0, SIMD<mask64,1> i1) { mask[0] = i0[0]; mask[1] = i1[0]; }
SIMD (float64x2_t _data) : mask{_data} { }
//SIMD (__m128i _mask) : mask(_mask) { ; }
auto Data() const { return mask; } auto Data() const { return mask; }
static constexpr int Size() { return 2; } static constexpr int Size() { return 2; }
// static NETGEN_INLINE SIMD<mask64, 2> GetMaskFromBits (unsigned int i); // static NETGEN_INLINE SIMD<mask64, 2> GetMaskFromBits (unsigned int i);
@ -37,26 +36,21 @@ namespace ngcore
static constexpr int Size() { return 2; } static constexpr int Size() { return 2; }
SIMD () {} SIMD () {}
SIMD (const SIMD &) = default; SIMD (const SIMD &) = default;
SIMD (double v0, double v1) { data[0] = v0; data[1] = v1; } // SIMD (double v0, double v1) : data{v0,v1} { }
SIMD (double v0, double v1) : data{vcombine_f64(float64x1_t{v0}, float64x1_t{v1})} { }
SIMD (std::array<double, 2> arr) SIMD (std::array<double, 2> arr) : data{arr[0], arr[1]} { }
// : data{(arr[0], arr[1])}
{
data[0] = arr[0];
data[1] = arr[1];
}
SIMD & operator= (const SIMD &) = default; SIMD & operator= (const SIMD &) = default;
SIMD (double val) { data[0] = data[1] = val; } SIMD (double val) : data{val,val} { }
SIMD (int val) { data[0] = data[1] = double(val); } SIMD (int val) : data{double(val),double(val)} { }
SIMD (size_t val) { data[0] = data[1] = double(val); } SIMD (size_t val) : data{double(val),double(val)} { }
SIMD (double const * p) SIMD (double const * p)
{ {
// data = vld1q_f64(p); data = vld1q_f64(p);
data[0] = p[0]; // data[0] = p[0];
data[1] = p[1]; // data[1] = p[1];
} }
SIMD (double const * p, SIMD<mask64,2> mask) SIMD (double const * p, SIMD<mask64,2> mask)
@ -75,9 +69,11 @@ namespace ngcore
void Store (double * p) void Store (double * p)
{ {
// vst1q_f64(p, data); vst1q_f64(p, data);
/*
p[0] = data[0]; p[0] = data[0];
p[1] = data[1]; p[1] = data[1];
*/
} }
void Store (double * p, SIMD<mask64,2> mask) void Store (double * p, SIMD<mask64,2> mask)
@ -86,7 +82,8 @@ namespace ngcore
if (mask[1]) p[1] = data[1]; if (mask[1]) p[1] = data[1];
} }
NETGEN_INLINE double operator[] (int i) const { return ((double*)(&data))[i]; } // NETGEN_INLINE double operator[] (int i) const { return ((double*)(&data))[i]; }
NETGEN_INLINE double operator[] (int i) const { return data[i]; }
NETGEN_INLINE auto Data() const { return data; } NETGEN_INLINE auto Data() const { return data; }
NETGEN_INLINE auto & Data() { return data; } NETGEN_INLINE auto & Data() { return data; }
@ -99,6 +96,7 @@ namespace ngcore
double Lo() const { return data[0]; } double Lo() const { return data[0]; }
double Hi() const { return data[1]; } double Hi() const { return data[1]; }
// __ai float64x1_t vget_high_f64(float64x2_t __p0) {
}; };
@ -133,14 +131,36 @@ namespace ngcore
return FNMA(SIMD<double,2> (a), b, c); return FNMA(SIMD<double,2> (a), b, c);
} }
NETGEN_INLINE SIMD<double,2> operator+ (SIMD<double,2> a, SIMD<double,2> b)
{ return a.Data()+b.Data(); }
NETGEN_INLINE SIMD<double,2> operator- (SIMD<double,2> a, SIMD<double,2> b)
{ return a.Data()-b.Data(); }
NETGEN_INLINE SIMD<double,2> operator- (SIMD<double,2> a)
{ return -a.Data(); }
NETGEN_INLINE SIMD<double,2> operator* (SIMD<double,2> a, SIMD<double,2> b)
{ return a.Data()*b.Data(); }
NETGEN_INLINE SIMD<double,2> operator/ (SIMD<double,2> a, SIMD<double,2> b)
{ return a.Data()/b.Data(); }
NETGEN_INLINE SIMD<double,2> If (SIMD<mask64,2> a, SIMD<double,2> b, SIMD<double,2> c) NETGEN_INLINE SIMD<double,2> If (SIMD<mask64,2> a, SIMD<double,2> b, SIMD<double,2> c)
{ {
return { a[0] ? b[0] : c[0], a[1] ? b[1] : c[1] }; // return { a[0] ? b[0] : c[0], a[1] ? b[1] : c[1] };
return vbslq_f64(a.Data(), b.Data(), c.Data());
} }
NETGEN_INLINE SIMD<int64_t,2> If (SIMD<mask64,2> a, SIMD<int64_t,2> b, SIMD<int64_t,2> c) NETGEN_INLINE SIMD<int64_t,2> If (SIMD<mask64,2> a, SIMD<int64_t,2> b, SIMD<int64_t,2> c)
{ {
return SIMD<int64_t,2> (a[0] ? b[0] : c[0], a[1] ? b[1] : c[1]); return SIMD<int64_t,2> (a[0] ? b[0] : c[0], a[1] ? b[1] : c[1]);
} }
NETGEN_INLINE SIMD<mask64,2> operator&& (SIMD<mask64,2> a, SIMD<mask64,2> b)
{
return vandq_u64 (a.Data(), b.Data());
}
} }